Our employer is looking for someone for the following position...

Director of Engineering- Physical Design

This is a senior engineering management position, reporting to the Vice President of Engineering. The person in this position has responsibility for delivering the semiconductor products in a timely, high quality, cost-effective manner. The individual must have demonstrated success in delivering complex digital and analog SoC, forming partnerships with CAD/EDA vendors and IP providers.

The individual in this position works closely with the operations group for DFT, packaging, foundry relations and manufacturing aspects of semiconductor products. The individual also works with product marketing group to evangelize and prioritize market/customer needs with required delivery dates.
The person must have deep technical knowledge and proven managerial expertise to lead, manage and grow physical design group of 7 engineers today.

Key Responsibilities
• Manages SOC designs, IP selection such as SERDES, memory, and other analog IP
• Drives Signal Integrity analysis, and Package design.
• Technical and management responsibilities to lead multiple tape outs.
• Negotiates aggressive & achievable product schedules, tracks them to completion, and provides clear status both within and outside the engineering group
• Ensures proper measurements and CAD/CAE tools are in place, especially methods and processes for delivering ‘right the first time’, production worthy, high volume silicon.
• The responsibility also spans into the low power area focusing on low power physical design flows and methodologies like Power Gating, Voltage scaling, Frequency scaling etc.
• Provides mentoring, motivation & career development to the team members
• Works closely with the Operations team integrating innovative Design for Testability measures to facilitate high volume production testing
• Owns and drives the right technology/foundry selection decision for optimal cost/performance

Knowledge/Skills/Experience:
• A minimum of 10 years of industry experience
• Familiar with Place and Route tools like Magma or Synopsys
• Experience with multiple chip tape outs and driving silicon to production
• Familiarity with Low Power designs
• Familiar with new technology issues in 65nm and beyond
• Prime Time STA tools and efficient Design flows and methodologies
• Package design and SI Issues at 5+ Gbps
• Experience of working with Silicon Foundries
• Experience of I/O interconnects standards and technologies such as PCI Express
• Ability to work cross-functionally within a relatively flat organization
• Driven self-starter; clear, logical thinker; bright and energetic; attention to detail
• Solid work ethic and strong time management that gets things done, on time, every time.

Education: BSEE is required, MSEE Preferred

Base Salary: $150K - $160K

Location: Sunnyvale, California (Silicon Valley)

Split Commission at 50/50 or 80/20 (candidate recruiter gets 80%)

Please contact me if you have good candidates! Thank you.

lisa.zee@enetrecruiter.com