Job Opening List for Telecom - Talents Needed

1.Senior/Principal Analog IC Design Engineer

Location: Santa Clara, CA

As a principal chip designer, the job function is to be responsible to architect analog modules, have good understanding of the design and verification

principles, provide guidance to junior engineers on design/simulation/layout, and perform reviews to improve the quality of delivery. He/she will also be

actively involved in silicon characterization, debugging, quality improving and releasing to production.


1. Master’s Degree or higher in Electrical Engineering or equivalent.

2. 5+ years experience on analog IC design, with at least two years experience on data converter design or high speed interface design, and having successful

mixed-signal design track record.

3. In-depth knowledge and design experience on at least one of following areas include high-speed/high-precision ADC/DAC, high speed SERDES/PHY,

ROM/RAM/EFLASH, high performance PLL, PMU. Knowledgeable on digital signal processing or ESD is a plus.

4. Ability to work in a team environment; self-motivated and inclined to take initiatives; and with excellent communication skills.

2.Senior CMOS RF IC Designer

Location: Santa Clara, CA

Architecture and implement RFIC design, perform system/circuit design and verification, supervise layout engineers on layout of RF/Analog circuits.


1. MSEE or PhD, approximately +3 years on RFIC design experience SiGe or RFCMOS experience.

2. Strong design experience with chip level system design and circuit design, such as LNA, mixer, PLL, VCO, filter, etc.

3. Familiar with RFIC design verification, tape out, debug and characterization

4. Good Knowledge about device modeling and RF system.

5. Candidates will display good development thinking ability, excellent communication skills, initiative, and a team attitude..

6. Experience on Zero IF WCDMA transceiver or GSM transceiver design or GSM Power amplifier is a plus

3.Video&Image Algorithm Expert (2 openings)

Location: Santa Clara/Shenzhen/Beijing

Algorithm design/analysis/modeling in video or image processing
BS or higher in EE/CS/Math
8+ years experience in video or image processing algorithm design
Experience in algorithm modeling or implementation of DSP processor in video standard protocols and graphics such as 2D/3D processing, image scalar, OSD,

image de-noise, AWB, AE, and AF

4.Multimedia SOC Principal Engineer

Location: Santa Clara, CA

Be responsible for requirement analysis, system analysis, architecture design and partition, analysis of performance trade-offs, issues and looking for ways

to improve architecture implementation and cost to achieve competition capability for the multimedia processing high performance SOC designs which will be

part of the next generation of video consumer electronics including high definition DVD players/recorders, Set-top Boxes and Digital TVs.

Minimum of 8 years experience in design of signal processing ICs.
Experience in the architecture/design of multimedia processors for consumer electronics, especially high definition DVD players / recorders, HD Set-top Boxes

and HD Digital TVs, is highly desirable.
Demonstrated ability to innovate and make architectural/design trade-offs for balancing performance/power/area of designs
Multimedia experience including one or more of camera, display, video codecs & standards, 2D & 3D graphics and multimedia processing is required.
System experience including system loading, MIPS analysis, interfaces, bandwidth optimization and STB architecture & digital video standards is also


5.Staff Analog Design Engineer --- Data Converter/AFE

Location: Santa Clara, CA

Roles and Responsibilities

Architect and implement analog and mixed-signal systems and circuits, such as ADCs, DACs, and Analog Front End (AFE). Responsibility includes circuit design,

simulation/verification, layout supervision, lab characterization/validation, and yield improvement.


1. At least 3 to 5 years’ analog IC design experience in a product development environment.

2. Strong silicon design experience in at least one of the following fields: high speed/high precision ADCs (pipelined/delta-sigma), high speed/high

precision DACs (current-steering/delta-sigma), analog filters, Programmable Gain Amplifiers (PGA), High-speed amplifiers/op-amps, and line drivers.

3. Knowledge/experience of data converter calibration (digital/analog) is a plus.

4. Good lab debugging skills is a plus.

5. Knowledge of Matlab/Simulink modeling and simulation is a plus.

6. MS or Ph.D. in Electrical Engineering or related disciplines.

6.Sr. SERDES Design Engineer

Location: Santa Clara, CA

Position Summary:
Our Serdes design team is seeking an outstanding team member to help us bring new products from design to market and provide fast, reliable solutions to our

customers. In this exciting role you will be designing sophisticated high-performance Serdes with our Serdes team to advance the technology solutions in the

ASIC market.

-Design and verify sophisticated mixed-signal analog blocks for high-speed SerDes such as PLL, CDR, Serializer, Deserializer, etc.
-Participate and be a key contributor in chip and block level architectures.
-Develop circuit schematics and perform all necessary verification/simulations.
-Assist in architecture, layout, integration, bring-up, post silicon debugging, and characterization.
-Generate design review documentation.
-Interface with other design team members and provide directions to layout and other design engineers, ensuring that electrical performance meets

specifications and requirements.
-Exchange information with, and provide guidance to, other team members in their daily activities.
-Resolve a wide range of issues; fully proficient in understanding of industry communication standards and test equipment tools.
-Self motivated team player.

-BS/MS/PhD Electrical Engineering, and Good communication skills.
-5+ years of analog circuit design experience, mostly in high-speed and low-jitter SERDES.
-Familiar with analog/mixed signal circuit design flow, hands-on experience in designing high speed (> 6.5GHz) analog circuits such as PLL, VCO, CDR, SERDES,

-Familiar with design techniques and trade-offs on reducing jitter and increasing operating frequency.
-Knowledge of physical layer.

Reply to

Thanks and best regards.
Jack Chang
440 N Wolfe Rd.
Sunnyvale, CA 94085

Views: 94


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